Considerations for phase accumulator design for direct digital frequency synthesizers

This paper reviews the approach of using a direct digital frequency synthesizer (DDFS) to generate high-resolution, fast switching frequencies for modern communication systems. Because these systems are required to have high speed and/or low power requirements, optimizing the phase accumulator (PA) component is a crucial design step. A mathematical model for estimating the speed-power tradeoffs of pipelined PAs will be presented. Simulations based on this model show that pipelining the PA to the maximum allowable number of stages provides the smallest latency, but at power consumptions significantly higher than a non-pipelined PA. The model can be used to estimate the optimal number of pipeline stages for given speed-power constraints.

[1]  Amir M. Sodagar,et al.  Parabolic approximation: a new method for phase to amplitude conversion in sine-output direct digital frequency synthesizers , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[2]  B. Gold,et al.  A digital frequency synthesizer , 1971 .

[3]  Dhamin Al-Khalili,et al.  Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[4]  Vladimir Stojanovic,et al.  Digital System Clocking: High-Performance and Low-Power Aspects , 2003 .

[5]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[6]  Valeriu Beiu,et al.  VLSI implementations of threshold logic-a comprehensive survey , 2003, IEEE Trans. Neural Networks.

[7]  E.K.F. Lee,et al.  Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter , 1999, IEEE J. Solid State Circuits.

[8]  Zhihe Zhou,et al.  High performance direct digital frequency synthesizers , 2003, Proceedings of the 15th Biennial University/Government/ Industry Microelectronics Symposium (Cat. No.03CH37488).

[9]  D. Al-Khalili,et al.  ROM size reduction with low processing cost for direct digital frequency synthesis , 2001, 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233).

[10]  Amir M. Sodagar,et al.  A pipelined ROM-less architecture for sine-output direct digital frequency synthesizers using the second-order parabolic approximation , 2001 .

[11]  Reto Zimmermann,et al.  Binary adder architectures for cell-based VLSI and their synthesis , 1997 .

[12]  V. Beiu,et al.  Ultra-fast noise immune CMOS threshold logic gates , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[13]  Venceslav F. Kroupa.  A Digital Frequency Synthesizer , 1999 .