Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction

Small delay defect (SDD) and aging-induced circuit failure are both prominent reliability concerns for nanoscale integrated circuits. Faster-than-at-speed testing is effective on SDD detection in manufacturing testing, which is always implemented by designing a suite of test signal generation circuits on the chip. Meanwhile, the integration of online aging sensors is becoming attractive in monitoring aging-induced delay degradation in the runtime. These design requirements, if implemented in separate ways, will increase the complexity of a reliable design and consume more die area. In this paper, a unified capture scheme is proposed to generate programmable clock signals for the detection of both SDDs and circuit aging. Our motivation arises from the observations that SDD detection and online aging prediction both need to capture circuit response ahead of the functional clock. The proposed aging-resistant design method enables the offline test circuit to be reused in online operations. Reversed short channel effect is also exploited to make the underlying circuit resilient to process variations. The proposed scheme is validated by intensive HSPICE simulations. Experimental results demonstrate the effectiveness in terms of low area, power, and performance overheads.

[1]  Ku He,et al.  Temperature-aware NBTI modeling and the impact of input vector control on performance degradation , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Mark Mohammad Tehranipoor,et al.  A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Sachin S. Sapatnekar,et al.  Impact of NBTI on SRAM read stability and design for reliability , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[4]  Kwang-Ting Cheng,et al.  New challenges in delay testing of nanometer, multigigahertz designs , 2004, IEEE Design & Test of Computers.

[5]  Adit D. Singh,et al.  Achieving high transition delay fault coverage with partial DTSFF scan chains , 2007, 2007 IEEE International Test Conference.

[6]  Vivek Chickermane,et al.  Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression , 2005, 14th Asian Test Symposium (ATS'05).

[7]  V. Narayanan,et al.  Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack , 2006, 2006 International Electron Devices Meeting.

[8]  Jacob A. Abraham,et al.  On-chip Programmable Capture for Accurate Path Delay Test and Characterization , 2008, 2008 IEEE International Test Conference.

[9]  Sachin S. Sapatnekar,et al.  NBTI-Aware Synthesis of Digital Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[10]  Songwei Pei,et al.  An on-chip clock generation scheme for faster-than-at-speed delay testing , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[11]  C. P. Ravikumar,et al.  At-speed transition fault testing with low speed scan enable , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[12]  Fan Yang,et al.  Statistical reliability analysis under process variation and aging effects , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[13]  Mark Mohammad Tehranipoor,et al.  Test-Pattern Grading and Pattern Selection for Small-Delay Defects , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[14]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[15]  Haihua Yan,et al.  Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[16]  Yu Hu,et al.  Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Mark Mohammad Tehranipoor,et al.  Timing-based delay test for screening small delay defects , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[18]  Jacob A. Abraham,et al.  Small-Delay Defect Detection in the Presence of Process Variations , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

[19]  Xiaowei Li,et al.  A unified online Fault Detection scheme via checking of Stability Violation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[20]  Bo Yang,et al.  Optimized Circuit Failure Prediction for Aging: Practicality and Promise , 2008, 2008 IEEE International Test Conference.

[21]  Xiao Liu,et al.  Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[22]  Yu Cao,et al.  The Impact of NBTI on the Performance of Combinational and Sequential Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[23]  A. Kerber,et al.  PBTI under dynamic stress: From a single defect point of view , 2011, 2011 International Reliability Physics Symposium.

[24]  Teresa L. McLaurin,et al.  The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[25]  Weiping Shi,et al.  K longest paths per gate (KLPG) test generation for scan-based sequential circuits , 2004, 2004 International Conferce on Test.

[26]  Yu Cao,et al.  An efficient method to identify critical gates under circuit aging , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[27]  João Paulo Teixeira,et al.  Programmable aging sensor for automotive safety-critical applications , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[28]  Kaustav Banerjee,et al.  Aging-resilient design of pipelined architectures using novel detection and correction circuits , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[29]  Huawei Li,et al.  Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction , 2005, Journal of Computer Science and Technology.

[30]  S. Reddy,et al.  Output Hazard-Free Transition Delay Fault Test Generation , 1998, 2009 27th IEEE VLSI Test Symposium.

[31]  Kaushik Roy,et al.  Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[32]  Yu Cao,et al.  Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[33]  Bo Yang,et al.  Statistical prediction of circuit aging under process variations , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[34]  John Keane,et al.  An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[35]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[36]  Toshiyuki Maeda,et al.  Invisible delay quality - SDQM model lights up what could not be seen , 2005, IEEE International Conference on Test, 2005..