Concurrent detection of power supply noise

We propose a methodology for the concurrent detection of power supply noise affecting a general synchronous system and exceeding a tolerance bound to be chosen according to the system's constraints. Our solution is based on a suitable self-checking scheme which concurrently monitors a signal of the system clock distribution network and which is, by design, able to provide an output error message upon the occurrence of power supply noise. The produced error indication can then be exploited to recover from the detected noise (thus guaranteeing system's correct operation), or to accomplish diagnosis. Our scheme negligibly impacts system's performance, features self-checking ability with respect to a wide set of possible internal faults and keeps on revealing concurrently the occurrence of power supply noise, despite the possible presence of noise affecting also ground.

[1]  Michael Nicolaidis Fault secure property versus strongly code disjoint checkers , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[3]  Dimitris Gizopoulos,et al.  An asynchronous totally self-checking two-rail code error indicator , 1996, Proceedings of 14th VLSI Test Symposium.

[4]  William C. Carter,et al.  Design of dynamically checked computers , 1968, IFIP Congress.

[5]  Edward J. McCluskey,et al.  "RESISTIVE SHORTS" WITHIN CMOS GATES , 1991, 1991, Proceedings. International Test Conference.

[6]  Cecilia Metra,et al.  On-Chip Clock Faults' Detector , 2002, J. Electron. Test..

[7]  Cecilia Metra,et al.  Sensing circuit for on-line detection of delay faults , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[8]  P. Larsson Power supply noise in future IC's: a crystal ball reading , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[9]  Kaushik Roy,et al.  Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[10]  Cecilia Metra,et al.  Compact and highly testable error indicator for self-checking circuits , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[11]  Cecilia Metra,et al.  Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines , 2000, IEEE Trans. Computers.

[12]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[13]  Vivek Tiwari,et al.  Inductive noise reduction at the architectural level , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[14]  Cecilia Metra,et al.  Self-checking scheme for the on-line testing of power supply noise , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[15]  Cecilia Metra,et al.  On-line detection of logic errors due to crosstalk, delay, and transient faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[16]  S. Koeppe,et al.  Optimal Layout to Avoid CMOS Stuck-Open Faults , 1987, 24th ACM/IEEE Design Automation Conference.

[17]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[18]  Cecilia Metra,et al.  On-line testing scheme for clock's faults , 1997, Proceedings International Test Conference 1997.