16 Bit Low Power High Speed RCA Using Various Adder Configurations

The operation of subtraction, multiplication, division and address calculation rely on the operation of addition . The adder which lies in the critical delay path determines the speed of the systems overall speed. In recent years the option of reducing the power consumption been gaining prominence. Low power high speed parameters has been achieved with the 28 CMOS 1 bit full adder circuit in 4 bit , 8 bit and 16 bit RCA.The circuits of 1-bit full adder and RCA in this paper has been designed using cadence virtuoso tool. Keyword Conventional Adder, Full Adder, Low Power, Ripple Carry Adder (RCA)

[1]  Mary Jane Irwin,et al.  Area-time-power tradeoffs in parallel adders , 1996 .

[2]  Mohamed I. Elmasry,et al.  Low-Power Digital VLSI Design: Circuits and Systems , 1995 .

[3]  Mohamed W. Allam,et al.  Low power implementation of fast addition algorithms , 1998, Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341).