Developing Compact Models for Passive Devices on IBM 45nm CMOS SOI Technology

The standard IBM 45 nm technology is widely adopted for industrial and academic purpose by integrates circuit designers. Original models provided by foundry are not accurate, which might cause inaccuracy in circuit simulations. Equivalent circuit models, using RLC elements to simulate electrical component, will effectively deliver their electrical performance. This study consists of four steps to construct these models. First, Cadence Virtuoso, the commercial circuit design software was used to run simulations and extract data for different device parameters. Second, analyzing tools, like Microsoft Excel or Matlab, are used to analyze the extracted data. Then, equations are written for each parameter. Finally, these models are implemented in the device descriptive language, Verilog-A and test circuits will be constructed to demonstrate the accuracy of the models. The accurate passive component models from this study will contribute to accelerating the circuit designing process and improving the accuracy of circuit simulations. KEYWORDS IBM, Simulation, Verilog-A, Circuit design REFERENCES Yu Cao, Robert A. Groves, and Xuejue Huang, “Frequency-Independent Equivalent-Circuit Model for On-Chip Spiral Inductors,” in Proc. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 3, MARCH 2003. W. Gao and Z. Yu, “Scalable compact circuit model and synthesis for RF CMOS spiral inductors,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 3, pp. 1055–1064, Mar. 2006.