Cost minimization of partitioning circuits with complex resource constraints in FPGAs
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Tsai-Ming Hsieh | Su-Fen Tseng | T. Hsieh | Yu-Chung Lin | Yu-Shan Hung | Yu-Chung Lin | Su-Fen Tseng | Yu-Shan Hung
[1] Martin D. F. Wong,et al. Network-flow-based multiway partitioning with area and pin constraints , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Krzysztof Kozminski,et al. Cost Minimization of Partitions into Multiple Devices , 1993, 30th ACM/IEEE Design Automation Conference.
[3] Martin D. F. Wong,et al. Circuit partitioning with complex resource constraints in FPGAs , 1998, FPGA '98.
[4] Andrew B. Kahng,et al. A General Framework For Vertex Orderings, With Applications To Netlist Clustering , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[5] J. Cong,et al. Multiway partitioning with pairwise movement , 1998, ICCAD '98.
[6] Martin D. F. Wong,et al. Network flow based multi-way partitioning with area and pin constraints , 1997, ISPD '97.
[7] Baldomir Zajc,et al. Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect , 1994, 31st Design Automation Conference.