A Method of Extracting Metal-Gate High-$k$ Material Parameters Featuring Electron Gate Tunneling Current Transition
暂无分享,去创建一个
[1] Dim-Lee Kwong,et al. Investigation of hole-tunneling current through ultrathin oxynitride/oxide stack gate dielectrics in p-MOSFETs , 2002 .
[2] G. Bersuker,et al. Comparison of effective work function extraction methods using capacitance and current measurement techniques , 2006, IEEE Electron Device Letters.
[3] Paul K. Hurley,et al. Determination of electron effective mass and electron affinity in HfO2 using MOS and MOSFET structures , 2009 .
[4] H.J. Lin,et al. High performance tantalum carbide metal gate stacks for nMOSFET application , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[5] S.K. Banerjee,et al. Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks , 2006, IEEE Transactions on Electron Devices.
[6] J. Kim,et al. Current transport in metal/hafnium oxide/silicon structure , 2002, IEEE Electron Device Letters.
[7] M. Heyns,et al. Determination of tunnelling parameters in ultra-thin oxide layer poly-Si/SiO2/Si structures , 1995 .
[8] B. Brar,et al. Direct extraction of the electron tunneling effective mass in ultrathin SiO2 , 1996 .
[9] C. Leroux,et al. Experimental investigation of transport mechanisms through HfO2 gate stacks in nMOS transistors , 2009, 2009 Proceedings of the European Solid State Device Research Conference.
[10] C. Cabral,et al. A method for measuring barrier heights, metal work functions and fixed charge densities in metal/SiO2/Si capacitors , 2002 .
[11] Mong-Song Liang,et al. A physical model for hole direct tunneling current in p/sup +/ poly-gate pMOSFETs with ultrathin gate oxides , 2000 .
[12] G. Salace,et al. Fowler–Nordheim conduction in polysilicon (n+)-oxide–silicon (p) structures: Limit of the classical treatment in the barrier height determination , 2001 .
[13] Seiichi Miyazaki,et al. Unified analytic model of direct and Fowler–Nordheim tunnel currents through ultrathin gate oxides , 2000 .
[14] Investigation of the Correlation Between Temperature and Enhancement of Electron Tunneling Current Through $\hbox{HfO}_{\bf 2}$ Gate Stacks , 2008, IEEE Transactions on Electron Devices.
[15] M. Trentzsch,et al. Tunneling Effective Mass of Electrons in Lightly N-Doped $\hbox{SiO}_{x} \hbox{N}_{y}$ Gate Insulators , 2008, IEEE Transactions on Electron Devices.
[16] Yoshitaka Tsunashima,et al. Determination of Band Alignment of Hafnium Silicon Oxynitride/Silicon (HfSiON/Si) Structures using Electron Spectroscopy , 2005 .
[17] Analytical modeling of tunneling current through SiO2–HfO2 stacks in metal oxide semiconductor structures , 2009 .
[18] Tunneling of holes observed at work function measurements of metal/HfO2/SiO2/n-Si gate stacks , 2010 .
[19] Chen-Yu Hsieh,et al. Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs , 2009, IEEE Transactions on Electron Devices.
[21] R. Chau,et al. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.
[22] Seiichi Miyazaki,et al. Analytic model of direct tunnel current through ultrathin gate oxides , 2000 .
[23] D. Kwong,et al. Modeling of tunneling currents through HfO2 and (HfO2)x(Al2O3)/sub 1-x/ gate stacks , 2003, IEEE Electron Device Letters.
[24] Mark Y. Liu,et al. A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array , 2008, 2008 IEEE International Electron Devices Meeting.