Flash A/D specifications for multi-bit /spl Delta//spl Sigma/ A/D converters

This paper presents a study of the nonidealities of the flash A/D converter used in a multi-bit delta-sigma A/D converter. While most papers on multi-bit converters focus on the linearity problem of the D/A converter in the feedback loop, the offset and hysteresis of the flash AD converter can become a performance-limiting factor in the design of these converters. The simulations presented in this paper show that the offset-requirement of the flash A/D can result in an increased power-consumption and a lower operation speed of the /spl Delta//spl Sigma/ converter.