Teaching pipelining and concurrency using hardware description languages

Relating to a previous simplified VHDL processor model, a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, USA. This paper first describes the pipeline processor model and its VHDL implementation. It then presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.