On-die CMOS leakage current sensor for measuring process variation in sub-90nm generations
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C.H. Kim | K. Roy | S. Borkar | R.K. Krishnamurthy | S. Hsu
[1] P. Bai,et al. A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell , 2002, Digest. International Electron Devices Meeting,.