Highlight of VLSI at research Berkeley
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[1] Carlo H. Séquin. Design and Layout Generation at the Symbolic Level , 1987 .
[2] David A. Patterson,et al. Architecture of SOAR: Smalltalk on a RISC , 1984, ISCA 1984.
[3] Emmanuel Katevenis,et al. Reduced instruction set computer architectures for VLSI , 1984 .
[4] James R. Larus,et al. SPUR: A VLSI Multiprocessor Workstation , 1985 .
[5] Uehara,et al. Optimal Layout of CMOS Functional Arrays , 1981 .
[6] Alberto Sangiovanni-Vincentelli,et al. Chameleon: A New Multi-Layer Channel Router , 1986, DAC 1986.
[7] Alberto Sangiovanni-Vincentelli,et al. Two-Dimensional Compaction by 'Zone Refining' , 1986, DAC 1986.
[8] Thomas W. Williams,et al. A logic design structure for LSI testability , 1977, DAC '77.
[9] Carlo H. Séquin,et al. A VLSI RISC , 1982, Computer.
[10] Alberto Sangiovanni-Vincentelli,et al. TimberWolf3.2: A New Standard Cell Placement and Global Routing Package , 1986, DAC 1986.