Performance of a Generic Non-blocking Packet Switch

Abstract This paper provides a general model to study the performance of a family of non-blocking packet switches. The switch size is N x N , and it employs both input and output queueing to resolve the output port contentions. The switch fabric has a speed advantage of C, 1 ≤ C ≤ N , over the I/O links. This speedup factor of C enables up to C packets to be delivered to the same output port simultaneously and they are queued at the output buffers until they are served by the output links, if more than C packets contend for the same output simultaneously, the excess packets are queued at the input buffers until they are served by the switch and delivered to their desired output ports. This paper analyzes the impact of the speedup factor on the switch performance. in particular, the maximum switch throughput and the average system delay for any given C are obtained. The results demonstrate that the switch can achieve 99% throughput with a modest speedup factor of 4.