A 1.2Gb/s/pin wireless superconnect based on inductive inter-chip signaling (IIS)

A wireless bus for stacked chips is designed with the interface using inductive coupling with metal spiral inductors. Transceiver circuits non-return-to-zero signaling are developed. Test chips stacked at a distance of 300/spl mu/m communicate at data rates of up to 1.2Gb/s/pin. Fabricated in 0.35/spl mu/m CMOS technology, TX and RX dissipation are 43 and 2.5mW, respectively.

[1]  K. Watanabe,et al.  Powder LSI: an ultra small RF identification chip for individual recognition applications , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[2]  Paul D. Franzon,et al.  4 Gbps high-density AC coupled interconnection , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[3]  K. Warner,et al.  Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[4]  D.D. Antono,et al.  1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..