Procedural Functional Partitioning for Low Power

Power consumption in VLSI systems has become a critical metric for design evaluation. Although power reduction techniques can be applied at every level of design abstraction, most techniques are applied to the lower levels such as the register-transfer or gate levels and are limited to reducing power only to a portion of the entire circuit. We demonstrate power reduction using a coarsegrained procedural functional partitioning technique. This technique allows us to easily partition the entire processor (controller and datapath) by separating entire procedures into several smaller, mutually exclusive, interacting processors at a much higher level of the design abstraction. Power reduction is accomplished because only one smaller processor needs to be active at a time. Our results show that procedural functional partitioning can reduce average power consumption by as much as 78% with an average of 51%.

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