Simulating Circuit-Level Simplifications on CNF

Boolean satisfiability (SAT) and its extensions have become a core technology in many application domains, such as planning and formal verification, and continue finding various new application domains today. The SAT-based approach divides into three steps: encoding, preprocessing, and search. It is often argued that by encoding arbitrary Boolean formulas in conjunctive normal form (CNF), structural properties of the original problem are not reflected in the CNF. This should result in the fact that CNF-level preprocessing and SAT solver techniques have an inherent disadvantage compared to related techniques applicable on the level of more structural SAT instance representations such as Boolean circuits. Motivated by this, various simplification techniques and intricate CNF encodings for circuit-level SAT instance representations have been proposed. On the other hand, based on the highly efficient CNF-level clause learning SAT solvers, there is also strong support for the claim that CNF is sufficient as an input format for SAT solvers. In this work we study the effect of CNF-level simplification techniques, focusing on SatElite-style variable elimination (VE) and what we call blocked clause elimination (BCE). We show that BCE is surprisingly effective both in theory and in practice on CNF formulas resulting from a standard CNF encoding for circuits: without explicit knowledge of the underlying circuit structure, it achieves the same level of simplification as a combination of circuit-level simplifications and previously suggested polarity-based CNF encodings. We also show that VE can achieve many of the same effects as BCE, but not all. On the other hand, it turns out that VE and BCE are indeed partially orthogonal techniques. We also study the practical effects of combining BCE and VE for reducing the size of formulas and on the running times of state-of-the-art SAT solvers. Furthermore, we address the problem of how to construct original witnesses to satisfiable CNF formulas when applying a combination of BCE and VE.

[1]  Paul B. Jackson,et al.  Clause Form Conversions for Boolean Circuits , 2004, SAT (Selected Papers.

[2]  Sanjit A. Seshia,et al.  Beaver: Engineering an Efficient SMT Solver for Bit-Vector Arithmetic , 2009, CAV.

[3]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[4]  Oliver Kullmann,et al.  On a Generalization of Extended Resolution , 1999, Discret. Appl. Math..

[5]  Lakhdar Sais,et al.  Recovering and Exploiting Structural Knowledge from CNF Formulas , 2002, CP.

[6]  Hilary Putnam,et al.  A Computing Procedure for Quantification Theory , 1960, JACM.

[7]  Armin Biere,et al.  Blocked Clause Elimination , 2010, TACAS.

[8]  Dhiraj K. Pradhan,et al.  NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances , 2004, SAT.

[9]  Armin Biere,et al.  Effective Preprocessing in SAT Through Variable and Clause Elimination , 2005, SAT.

[10]  Allen Van Gelder,et al.  Toward leaner binary-clause reasoning in a satisfiability solver , 2005, Annals of Mathematics and Artificial Intelligence.

[11]  Daniel Le Berre Exploiting the real power of unit propagation lookahead , 2001, Electron. Notes Discret. Math..

[12]  Oliver Kullmann,et al.  New Methods for 3-SAT Decision and Worst-case Analysis , 1999, Theor. Comput. Sci..

[13]  Roberto Bruttomesso,et al.  The OpenSMT Solver , 2010, TACAS.

[14]  Ronen I. Brafman,et al.  A simplifier for propositional formulas with many binary clauses , 2001, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[15]  Alan Mishchenko,et al.  Applying Logic Synthesis for Speeding Up SAT , 2007, SAT.

[16]  David A. Plaisted,et al.  A Structure-Preserving Clause Form Translation , 1986, J. Symb. Comput..

[17]  Harry Zhang,et al.  Combining Adaptive Noise and Look-Ahead in Local Search for SAT , 2007, SAT.

[18]  Alan Bundy,et al.  Constructing Induction Rules for Deductive Synthesis Proofs , 2006, CLASE.

[19]  Ofer Strichman,et al.  Cost-Effective Hyper-Resolution for Preprocessing CNF Formulas , 2005, SAT.

[20]  David L. Dill,et al.  A Decision Procedure for Bit-Vectors and Arrays , 2007, CAV.

[21]  Fahiem Bacchus,et al.  Enhancing Davis Putnam with extended binary clause reasoning , 2002, AAAI/IAAI.

[22]  Paul W. Purdom,et al.  Solving Satisfiability with Less Searching , 1984, IEEE Transactions on Pattern Analysis and Machine Intelligence.

[23]  Fabio Somenzi,et al.  An Incremental Algorithm to Check Satisfiability for Bounded Model Checking , 2005, Electron. Notes Theor. Comput. Sci..

[24]  G. S. Tseitin On the Complexity of Derivation in Propositional Calculus , 1983 .

[25]  Cesare Tinelli,et al.  Satisfiability Modulo Theories , 2021, Handbook of Satisfiability.

[26]  Marijn J. H. Heule,et al.  Exact DFA Identification Using SAT Solvers , 2010, ICGI.

[27]  Toby Walsh,et al.  Handbook of satisfiability , 2009 .

[28]  Panagiotis Manolios,et al.  Efficient Circuit to CNF Conversion , 2007, SAT.

[29]  Theo Tryfonas,et al.  Frontiers in Artificial Intelligence and Applications , 2009 .

[30]  Panagiotis Manolios,et al.  Faster SAT solving with better CNF generation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[31]  Pedro Barahona,et al.  PSICO: Solving Protein Structures with Constraint Programming and Optimization , 2002, Constraints.

[32]  Rolf Drechsler,et al.  Non-Clausal SAT and ATPG , 2009, Handbook of Satisfiability.

[33]  Roberto Bruttomesso,et al.  The MathSAT 4 SMT Solver ( Tool Paper ) , 2008 .

[34]  Fabio Somenzi,et al.  On-the-Fly Clause Improvement , 2009, SAT.

[35]  Fahiem Bacchus,et al.  Effective Preprocessing with Hyper-Resolution and Equality Reduction , 2003, SAT.

[36]  Fabio Somenzi,et al.  Alembic: An Efficient Algorithm for CNF Preprocessing , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[37]  Armin Biere,et al.  Blocked Clause Elimination for QBF , 2011, CADE.

[38]  Armin Biere,et al.  Verifiying Safety Properties of a Power PC Microprocessor Using Symbolic Model Checking without BDDs , 1999, CAV.

[39]  Armin Biere,et al.  Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays , 2009, TACAS.

[40]  Hans van Maaren,et al.  Aligning CNF- and Equivalence-reasoning , 2004, SAT.

[41]  Thierry Boy de la Tour An Optimality Result for Clause Form Translation , 1992, J. Symb. Comput..

[42]  Hao Wang,et al.  Towards feasible solutions of the tautology problem , 1976 .

[43]  Armin Biere,et al.  Reconstructing Solutions after Blocked Clause Elimination , 2010, SAT.

[44]  Inês Lynce,et al.  The Interaction Between Simplification and Search in Propositional Satisfiability , 2001 .

[45]  Armin Biere,et al.  Compressing BMC Encodings with QBF , 2007, BMC@FLoC.

[46]  Bart Selman,et al.  Balance and Filtering in Structured Satisfiable Problems , 2001, IJCAI.

[47]  Holger H. Hoos,et al.  UBCSAT: An Implementation and Experimentation Environment for SLS Algorithms for SAT & MAX-SAT , 2004, SAT.

[48]  Jinbo Huang,et al.  Extended clause learning , 2010, Artif. Intell..

[49]  Gilles Audemard,et al.  A Restriction of Extended Resolution for Clause Learning SAT Solvers , 2010, AAAI.

[50]  Nikolaj Bjørner,et al.  Z3: An Efficient SMT Solver , 2008, TACAS.

[51]  B. Dunham,et al.  A non-heuristic program for proving elementary logical theorems , 1959, IFIP Congress.