A Binary Quantized Digital Phase Locked Loop: A Graphical Analysis

A non-uniform sampling digital phase locked loop (DPLL), with a hard limiter as quantizer, is analyzed by a graphical method in the case of phase and frequency step inputs and no noise. The cycle slipping and the limit cycles phenomena are investigated. An upper-bound to the model gain and, consequently, to the pull-in range is obtained. Also a closed-form expression of acquisition time is derived. Moreover, using a random-walk model, the stationary phase error variance, the mean acquisition time and the mean first slip time have been evaluated. Some two channel configurations are proposed, which allow us to obtain a faster acquisition. Finally the problems relevant to the practical implementation of the loop are analyzed.