Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations
暂无分享,去创建一个
[1] Mario Pinto-Guedes,et al. A circuit simulation model for bipolar-induced breakdown in MOSFET , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Siegfried Selberherr,et al. Analysis of Breakdown Phenomena in MOSFET's , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] A. Amerasekera,et al. Electrothermal behavior of deep submicron nMOS transistors under high current snapback (ESD/EOS) conditions , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.
[4] S. L. Miller. Ionization Rates for Holes and Electrons in Silicon , 1957 .
[5] Sung-Mo Kang,et al. Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.
[6] S.E. Laux,et al. A study of channel avalanche breakdown in scaled n-MOSFET's , 1987, IEEE Transactions on Electron Devices.
[7] R.W. Dutton,et al. Bipolar transistor modeling of avalanche generation for computer circuit simulation , 1975, IEEE Transactions on Electron Devices.
[8] J.R.M. Luchies,et al. Fast turn-on of an NMOS ESD protection transistor: measurements and simulations , 1995 .
[9] M. Reisch. On bistable behavior and open-base breakdown of bipolar transistors in the avalanche regime-modeling and applications , 1992 .
[10] J. Moll,et al. Breakdown mechanism in short-channel MOS transistors , 1978, 1978 International Electron Devices Meeting.
[11] J. Lindmayer,et al. Theory of lateral transistors , 1967 .
[12] Sung-Mo Kang,et al. Circuit-Level Electrothermal Simulation , 1995 .
[13] S. Asai,et al. A numerical model of avalanche breakdown in MOSFET's , 1978, IEEE Transactions on Electron Devices.
[14] E. Worley,et al. Sub-micron chip ESD protection schemes which avoid avalanching junctions , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.
[15] G. Groeseneken,et al. A compact model for the grounded-gate nMOS behaviour under CDM ESD stress , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.
[16] S. Simon Wong,et al. High-gain lateral bipolar action in a MOSFET structure , 1991 .
[17] A. Amerasekera,et al. Characterization and modeling of second breakdown in NMOST's for the extraction of ESD-related process and design parameters , 1991 .
[18] Kueing-Long Chen. The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors , 1988 .
[19] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[20] B. Eitan,et al. Surface conduction in short-channel MOS devices as a limitation to VLSI scaling , 1982, IEEE Transactions on Electron Devices.
[21] R. Muller,et al. VIA-4 avalanche-induced breakdown mechanisms in short-channel MOSFETs , 1982, IEEE Transactions on Electron Devices.
[22] N. D. Jankovic. Pre-turn-on source bipolar injection in graded NMOSTs , 1991 .
[23] C. Duvvury,et al. Dynamic gate coupling of NMOS for efficient output ESD protection , 1992, 30th Annual Proceedings Reliability Physics 1992.
[24] Christian Russ,et al. Compact electro‐thermal simulation of ESD‐protection elements , 1994 .
[25] Chenming Hu,et al. An analytical breakdown model for short-channel MOSFET's , 1982, IEEE Transactions on Electron Devices.
[26] Theodore I. Kamins,et al. Device Electronics for Integrated Circuits , 1977 .
[27] A. G. Chynoweth,et al. Uniform Silicon p‐n Junctions. II. Ionization Rates for Electrons , 1960 .