A Verification Guide for the Perplexed Designer: Matching Verification Techniques and Design Tasks

Several techniques and tools for “formal verification” of hardware designs currently exist and others are rapidly evolving. The more widely known examples include Boolean tautology checkers, algorithms for proving state-machine equivalence, techniques based on temporal logic model-checking, and interactive theoremproving based methods; in addition, many more variations and approaches exist, e.g., [l], [4]. Many of these techniques seem superficially quite different and unrelated, often involving different types of inputs, different levels and kinds of user interaction (or interfaces), different underlying theoretical models, and different algorithms. Moreover, many of these techniques and tools are not yet properly coupled to existing computeraided design (CAD) environments or do not (at first sight) mesh well with conventional hardware design paradigms. To the uninitiated system designer, and quite frequently, even to the verification conscious designer, the assortment of techniques and tools seem bewildering to sort through and understand. This detracts considerably from the use of such techniques; further, it makes it unclear what directions of research might be more fruitful.