A low energy dual-mode adder

VLSI designs are typically data-independent and as such, they must produce the correct result even for the worst-case inputs. Adders in particular assume that addition must be completed within prescribed number of clock cycles, independently of the operands. While the longest carry propagation of an n-bit adder is n bits, its expected length is only O(log"2n) bits. We present a novel dual-mode adder architecture that reduces the average energy consumption in up to 50%. In normal mode the adder targets the O(log"2n)-bit average worst-case carry propagation chains, while in extended mode it accommodates the less frequent O(n)-bit chain. We prove that minimum energy is achieved when the adder is designed for O(log"2n) carry propagation, and present a circuit implementation. Dual-mode adders enable voltage scaling of the entire system, potentially supporting further overall energy reduction. The energy-time tradeoff obtained when incorporating such adders in ordinary microprocessor's pipeline and other architectures is discussed.

[1]  Steven M. Nowick.  Design of a low-latency asynchronous adder using speculative completion , 1996 .

[2]  Luca Benini,et al.  Telescopic units: a new paradigm for performance optimization of VLSI designs , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Yiran Chen,et al.  Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  David Blaauw,et al.  Razor: circuit-level correction of timing errors for low-power operation , 2004, IEEE Micro.

[5]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[6]  Kaushik Roy,et al.  Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Israel Koren.  Computer arithmetic algorithms , 1993 .

[8]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[9]  Jeffrey D Ullma.  Computational Aspects of VLSI , 1984 .

[10]  Alain J. Martin.  Asynchronous datapaths and the design of an asynchronous adder , 1992, Formal Methods Syst. Des..

[11]  Keshab K. Parhi,et al.  Estimation of average energy consumption of ripple-carry adder based on average length carry chains , 1996, VLSI Signal Processing, IX.

[12]  Peter A. Beerel,et al.  Speculative completion for the design of high-performance asynchronous dynamic adders , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[13]  Stephen H. Unger,et al.  Self-Timed Carry-Lookahead Adders , 2000, IEEE Trans. Computers.

[14]  Mark Horowitz,et al.  Self-timed logic using Current-Sensing Completion Detection (CSCD) , 1994, J. VLSI Signal Process..

[15]  Ivan E. Sutherland,et al.  The counterflow pipeline processor architecture , 1994, IEEE Design & Test of Computers.

[16]  Marly Roncken,et al.  Asynchronous circuits for low power: a DCC error corrector , 1994, IEEE Design & Test of Computers.

[17]  Keshab K. Parhi,et al.  Theoretical estimation of power consumption in binary adders , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[18]  Puneet Gupta,et al.  Trading Accuracy for Power with an Underdesigned Multiplier Architecture , 2011, 2011 24th Internatioal Conference on VLSI Design.