Static Optimal Scheduling for Synchronous Data Flow Graphs with Model Checking
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[1] Amit Kumar Singh,et al. Mapping on multi/many-core systems: Survey of current and emerging trends , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[2] Shuvra S. Bhattacharyya,et al. Embedded Multiprocessors: Scheduling and Synchronization, Second Edition , 2009 .
[3] Rudy Lauwereins,et al. Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets , 1997, DAC.
[4] Frank D. Valencia,et al. Formal Methods for Components and Objects , 2002, Lecture Notes in Computer Science.
[5] Robert Grimm,et al. A catalog of stream processing optimizations , 2014, ACM Comput. Surv..
[6] Keshab K. Parhi,et al. Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding , 1991, IEEE Trans. Computers.
[7] Achim Rettberg,et al. Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[8] Shuvra S. Bhattacharyya,et al. Embedded Multiprocessors: Scheduling and Synchronization , 2000 .
[9] Ge Yu,et al. Static Scheduling and Software Synthesis for Dataflow Graphs with Symbolic Model-Checking , 2007, RTSS 2007.
[10] Eugene Asarin,et al. Scheduling with timed automata , 2006, Theor. Comput. Sci..
[11] Edward A. Lee,et al. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.
[12] Sander Stuijk,et al. Throughput-Buffering Trade-Off Exploration for Cyclo-Static and Synchronous Dataflow Graphs , 2008, IEEE Transactions on Computers.
[13] David Gregg,et al. Orchestrating stream graphs using model checking , 2013, ACM Trans. Archit. Code Optim..
[14] Michael R. Hansen,et al. System-level Verification of Multi-Core Embedded Systems using Timed-Automata , 2008 .
[15] Kim G. Larsen,et al. Quantitative analysis of real-time systems using priced timed automata , 2011, Commun. ACM.
[16] Fausto Giunchiglia,et al. NUSMV: a new symbolic model checker , 2000, International Journal on Software Tools for Technology Transfer.
[17] Gerard J. Holzmann,et al. The Model Checker SPIN , 1997, IEEE Trans. Software Eng..
[18] Ge Yu,et al. Static Scheduling and Software Synthesis for Dataflow Graphs with Symbolic Model-Checking , 2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007).
[19] Sander Stuijk,et al. Minimising buffer requirements of synchronous dataflow graphs with model checking , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[20] Sander Stuijk,et al. Static Rate-Optimal Scheduling of Multirate DSP Algorithms via Retiming and Unfolding , 2012, 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium.
[21] Joost-Pieter Katoen,et al. Model checking of Scenario-Aware Dataflow with CADP , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[22] Wang Yi,et al. Uppaal in a nutshell , 1997, International Journal on Software Tools for Technology Transfer.
[23] Pieter H. Hartel,et al. Scheduling Optimisations for SPIN to Minimise Buffer Requirements in Synchronous Data Flow , 2008, 2008 Formal Methods in Computer-Aided Design.
[24] Rajeev Alur,et al. A Theory of Timed Automata , 1994, Theor. Comput. Sci..
[25] Kim G. Larsen,et al. Priced Timed Automata: Algorithms and Applications , 2004, FMCO.
[26] Marco Caccamo,et al. Toward the Predictable Integration of Real-Time COTS Based Systems , 2007, RTSS 2007.
[27] Wang Yi,et al. Schedulability analysis of fixed-priority systems using timed automata , 2006, Theor. Comput. Sci..
[28] John P. Lehoczky,et al. Timing Analysis for Fixed-Priority Scheduling of Hard Real-Time Systems , 1994, IEEE Trans. Software Eng..