A Wide-Range and High PSRR CMOS Voltage Reference for Implantable Device

This paper presents a design of a high power supply rejection ratio (PSRR) voltage reference used in an implantable device. The coupling ripple noise from the power supply in implantable device can be reduced by a modified design of wide-bandwidth PSRR VGS voltage reference with negative feedback schemes. The circuit has been verified by using TSMC 0.35mum mixed-signal 2P4M polycide 3.3/5V models. The simulation results show the proposed circuit improves PSRR up to 80dB at 1 MHz and only consumes 23.6muW at 3V power supply. The circuit not only maintains the same performance as the conventional Vgs-reference but also is suitable for high input power supply

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