On latching probability of particle induced transients in combinational networks
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[1] Marcus Rimén,et al. A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection , 1992, Proceedings International Test Conference 1992.
[2] Johan Karlsson,et al. Using heavy-ion radiation to validate fault-handling mechanisms , 1994, IEEE Micro.
[3] J. G. Tront,et al. An HDL Simulation of the Effects of Single Event Upsets on Microprocessor Program Flow , 1984, IEEE Transactions on Nuclear Science.
[4] Elizabeth M. Rudnick,et al. A fast and accurate gate-level transient fault simulation environment , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.
[5] Resve Saleh,et al. Simulation and analysis of transient faults in digital circuits , 1992 .
[6] P. Liden,et al. Efficient modeling of switch-level networks containing undetermined logic node states , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[7] G. C. Messenger,et al. Collection of Charge on Junction Nodes from Ion Tracks , 1982, IEEE Transactions on Nuclear Science.
[8] Janak H. Patel,et al. A logic-level model for /spl alpha/-particle hits in CMOS circuits , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.
[9] Victor Carreño,et al. Simulated fault injection: a methodology to evaluate fault tolerant microprocessor architectures , 1990 .
[10] Daniel G. Saab,et al. Fault behavior dictionary for simulation of device-level transients , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).