Evaluating Coverage of Error Detection Logic for Soft Errors using Formal Methods

In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and -correction logic. We describe an easily portable approach, which can be applied to a wide variety of multi-GHz industrial designs

[1]  J. J. Serrano,et al.  Experimental validation of high-speed fault-tolerant systems using physical fault injection , 1999, Dependable Computing for Critical Applications 7.

[2]  Régis Leveugle,et al.  A new approach for early dependability evaluation based on formal property checking and controlled mutations , 2005, 11th IEEE International On-Line Testing Symposium.

[3]  Matthias Pflanz.  Online Fehler-Erkennung und schnelle Wiederherstellungs-Techniken für zuverlässige eingebettete Prozessoren (Online Error Detection and Fast Recover Techniques for Dependable Embedded Processors) , 2004, it Inf. Technol..

[4]  T. Calin,et al.  SEU-hardened storage cell validation using a pulsed laser , 1996 .

[5]  Johan Karlsson,et al.  A comparison of simulation based and scan chain implemented fault injection , 1998, Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224).

[6]  Suchai Thanawastien,et al.  An SFS Berger check prediction ALU and its application to self-checking processor designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Christian Jacobi,et al.  Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting , 2005, CHARME.

[8]  Kewal K. Saluja,et al.  Event-centric simulation of crosstalk pulse faults in sequential circuits , 2003, Proceedings 21st International Conference on Computer Design.

[9]  M. Pflanz,et al.  On-line error detection techniques for dependable embedded processors with high complexity , 2001, Proceedings Seventh International On-Line Testing Workshop.

[10]  Cristian Constantinescu,et al.  Experimental evaluation of error-detection mechanisms , 2003, IEEE Trans. Reliab..

[11]  Jason Baumgartner,et al.  Automatic formal verification of fused-multiply-add FPUs , 2005, Design, Automation and Test in Europe.

[12]  Wilfrido Alejandro Moreno,et al.  Validating fault tolerant designs using laser fault injection (LFI) , 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[13]  Parag K. Lala,et al.  Fault injection for verifying testability at the VHDL level , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[14]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.