A 150 MIPS/W CMOS RISC processor for PDA applications

This CMOS microprocessor has performance of about 45MIPS at 50 MHz with about 300 mW power dissipation at 3.3 V power supply. It implements about 440 k transistors in a 25 mm/sup 2/ die fabricated by 0.41 /spl mu/m double metal CMOS. It is designed as a core processor for PDA applications, that require high speed graphical operation and digital signal processing functions as well as low power consumption from portability requirements.

[1]  Toshinori Sato,et al.  Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.