A 150 MIPS/W CMOS RISC processor for PDA applications
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Masato Nagamatsu | Hiroaki Murakami | Kamran Malik | A. Kawasumi | M. Kamata | H. Tago | T. Mijamori | Y. Ootaguro | H. Goto | T. Utsumi | Tatsuo Teruyama | K. Mabuchi
[1] Toshinori Sato,et al. Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.