Design optimization of analog integrated circuits by using artificial neural networks

This paper presents a computer-aided design (CAD) tool for automated sizing and optimization of analog integrated circuits (ICs). This tool uses artificial neural networks (ANNs) in order to deduce the device sizes that optimize the performance objectives while satisfying the constraint specifications. Neural networks can learn and generalize from data allowing model development even when component formulas are unavailable. The training data are obtained by various simulations in the HSPICE design environment with TSMC 0.18 μm CMOS process parameters. To evaluate the tool, one practical example is presented in 0.18 μm CMOS technology. The simulation results verify effectiveness of the proposed method for analog circuits sizing.

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