Model-based performance analysis for reconfigurable coprocessors

Uni-processor and shared memory UMA multi-processor workstations are currently ubiquitous. The capabilities of such machines are commonly extended through the use of one or more application-specific coprocessors, located on the system expansion/peripheral bus, or a dedicated local bus. It is therefore considered worthwhile to investigate the limits of applicability of FPGA-based reconfigurable coprocessors when used to enhance such machines. In order to do this, it must be possible to estimate performance for coprocessor architectures that do not currently exist. This paper describes a method for generating estimates of performance for applications which make use of such reconfigurable coprocessors. By combining direct measurements on the target platform with model-based estimates and simulation data, estimates of performance can be synthesised which are accurate to better than +/- 5%.