A study of relation between a power supply ESD and parasitic capacitance

In this study, we show that increased parasitic capacitance across lateral NPN (LNPN) devices does not necessarily enhance the electro-static discharge (ESD) robustness. Since the drain-bulk displacement current decreases, the LNPN avalanche trigger current increases and the PN junctions fail early. In our case, this happened when the parasitic capacitance between supply lines is around many hundreds of Pico-Farad.

[1]  T. Suzuki,et al.  ESD and latch-up characteristics of semiconductor device with thin epitaxial substrate , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[2]  C. Duvvury,et al.  The impact of technology scaling on ESD robustness and protection circuit design , 1995 .

[3]  B. Keppens,et al.  Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[4]  T. Suzuki,et al.  A study of fully silicided 0.18 /spl mu/m CMOS ESD protection devices , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[5]  Christian Russ,et al.  ESD protection elements during HBM stress tests: further numerical and experimental results , 1995 .