P‐140: A Modified Selective Reset‐Waveform to Minimize Wall‐Voltage Variation During Address‐Period in Full‐HD PDP

This paper proposes a modified selective reset driving waveform that can lower the potential difference between the scan and address electrodes by applying the address-bias voltage (Va-bias) to the address electrode during the application of the rising pulse of Y-electrode in the selective reset-period. This address-bias voltage (Va-bias) plays a role in suppressing the wall-charge accumulation on the address electrode during the selective reset-period, thereby contributing to minimizing the wall-voltage variation during the address-period and as such allowing the higher voltage difference (=ΔVy) between the scan low voltage (Vsl) and the negative falling ramp voltage (Vnf) during an address-period without any misfiring discharge. When adopting the proposed selective reset waveform, the address discharge delay time is observed to be reduced by about 120 ns.