Biconditional-BDD Ordering for Autosymmetric Functions

Autosymmetric functions are particular "regular" Boolean functions that are exploited for logic optimization, since it is possible to reduce the number of variables and the number of points of the original autosymmetric function before its synthesis. In this paper we study this regularity in oder to derive a suitable variable ordering for Biconditional Binary Decision Diagrams (BBDDs). BBDDs are a new version of BDD that have EXOR of two variables (instead of a variable) in the nodes. These diagrams are employed for logic synthesis in new technologies such as silicon nanowires and DG-SiNWFETs. We show that it is possible to find a useful variable ordering for these functions and the experimental results validate our approach showing that in the 97% of the cases we get an ordering that gives a number of nodes that is lower or equal to the one obtained with the standard ordering.

[1]  Karem A. Sakallah,et al.  Generalized symmetries in Boolean functions , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[2]  Fabrizio Luccio,et al.  On a New Boolean Function with Applications , 1999, IEEE Trans. Computers.

[3]  Giovanni De Micheli,et al.  Biconditional BDD: A novel canonical BDD for logic synthesis targeting XOR-rich circuits , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Tsutomu Sasao,et al.  A New Expansion of Symmetric Functions and Their Application to Non-Disjoint Functional Decompositions for LUT Type FPGAs , 2000 .

[5]  Fabrizio Luccio,et al.  Synthesis of Autosymmetric Functions in a New Three-Level Form , 2007, Theory of Computing Systems.

[6]  Paul Molitor,et al.  Least Upper Bounds for the Size of OBDDs Using Symmetry Properties , 2000, IEEE Trans. Computers.

[7]  Tsutomu Sasao,et al.  Switching Theory for Logic Synthesis , 1999, Springer US.

[8]  Enrico Macii,et al.  One-pass logic synthesis for graphene-based Pass-XNOR logic circuits , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[9]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[10]  Karem A. Sakallah,et al.  Constructive library-aware synthesis using symmetries , 2000, DATE '00.

[11]  Giovanni De Micheli,et al.  Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[12]  Valentina Ciriani A New Approach to Three-Level Logic Synthesis , 2002 .

[13]  Fabrizio Luccio,et al.  Three-level logic minimization based on function regularities , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Rolf Drechsler,et al.  BDD based synthesis of symmetric functions with full path-delay fault testability , 2003, 2003 Test Symposium.

[15]  Fabrizio Luccio,et al.  Exploiting Regularities for Boolean Function Synthesis , 2004, Theory of Computing Systems.

[16]  Giovanni De Micheli,et al.  Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization , 2015, ACM Great Lakes Symposium on VLSI.

[17]  Robert K. Brayton,et al.  ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.

[18]  Fabio Somenzi,et al.  CUDD: CU Decision Diagram Package Release 2.2.0 , 1998 .

[19]  Fabrizio Luccio,et al.  Implicit Test of Regularity for Not Completely Specified Boolean Functions , 2002, IWLS.

[20]  Fabrizio Luccio,et al.  Fast three-level logic minimization based on autosymmetry , 2002, DAC '02.

[21]  Igor L. Markov,et al.  Solving difficult SAT instances in the presence of symmetry , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[22]  Giovanni De Micheli,et al.  An efficient manipulation package for Biconditional Binary Decision Diagrams , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).