Low Power Soc Communication Using Steiner Graph AMBA Architecture

Reduction in size of a chip leads to more sophisticated design, but the system components must be designed to operate with considerably low power. Altering the data and control path in a design will reduce the power dissipation in a chip to a greater extent. The limitation of an normal bus design is that data or control values will be transmitted to all the Soc components invariably, thus the chip select control lies within the components, either single or many circuit will be activated with the reference to control signal but the transmission cost is high due to the unnecessary passage of signal in the bus path. Steiner graph method of predicting the best bus routing path combined with Gated clock tree structure, which will further make the design more flexible. The bus implementation is done by using AHB Bus protocol for its robust and flexible design in nature. Thus a low power operating Soc can be designed and implemented without modifying the structure of component but by altering bus path structure. The level of power consumption can be further reduced by modifying the structure of the components too.