A single-chip 16-bit 25 ns realtime video/image signal processor

A single-chip real-time video/image processor (VISP) has been developed that integrates functions based on a variable seven-stage pipeline arithmetic architecture in a 16-bit fixed-point data format. A three-input adder implemented in complementary CMOS reduced-swing logic, which is twice as fast as conventional CMOS logic, achieving a 25-ns instruction cycle, is shown. Single-VISP processing times are: edge detection (3*3 Laplacian), 14.8 ms; distance calculation, 1.7 ms; temporal filtering (1-tap IR), 5.0 ms; linear quantization, 3.3 ms; and 3/5*3/5 picture reduction (separate 5-tap FIR), 5.9 ms. An example is shown of a two-dimensional discrete cosine transformation which requires 26.3 ms to execute with one VISP when 256*256 pixel processing at a 25-ns instruction cycle is employed.<<ETX>>

[1]  Shinya Ohba,et al.  A 20-ns CMOS micro DSP core for video-signal processing , 1988 .

[2]  Takao Nishitani,et al.  A realtime microprogrammable video signal LSI , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  K. Kaneko,et al.  A 20ns Cmos Dsp Core For Video-signal Processing , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[4]  Yukio Endo,et al.  A single-board video signal processor module employing newly developed LSI devices , 1988, IEEE J. Sel. Areas Commun..

[5]  Takao Nishitani,et al.  Video signal processor configuration by multiprocessor approach , 1986, ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[6]  Yukio Endo,et al.  Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP , 1989, J. VLSI Signal Process..