Response surface modeling of 100 nm CMOS process technology using design of experiment

100 nm CMOS technology has been characterized through Design of Experiment (DOE) and statistical modeling. Initially, a set of 21 process parameters (factors) have been identified to determine their impact on transistor performance metrics such as threshold voltage V/sub t/, sub-threshold slope SS, drive current I/sub ddrive/, leakage current I/sub dbleak/, both in saturation and linear region. Through first order linear modeling of V/sub t/, SS, I/sub drive/, and I/sub dbleak/, a subset of 10 most significant process parameters are picked using Plackett-Burman screening experiment for both NMOS and PMOS devices. Significant process parameters which impact the device characteristics are seen to be different, for NMOS and PMOS devices, inspite of a common process flow. Response surfaces (RS) have been built in terms of these 10 parameters for NMOS device. Statistical parameters of the device characteristics fluctuations like mean(/spl mu/) and standard deviation (/spl sigma/) for V/sub t/, SS, I/sub ddrive/, I/sub dbleak/ and G/sub m/ (maximum transconductance), have been determined by Monte Carlo (MC) analysis of these response surfaces. Application of the Transmission of Moment Technique (TMT) on these models is shown to be a simple means to determine /spl mu/ and /spl sigma/ of the device characteristics, with simple mathematical calculations.