Programmable Logic Array Design for H.264 Context-Based Adaptive Variable Length Coding

In this paper, we propose an architecture for context-based adaptive variable length coding using programmable logic array. This design is focused in optimizing the hardware cost and enhancing the speed of encoding. The proposed architecture has been simulated using ModelSim, and implemented by UMC 0.18 mum cell library. Simulation results illustrates that, the proposed design satisfies the real time constrains, required by various video applications with 2475 logic gates at 210 MHz

[1]  Wu Di,et al.  A VLSI architecture design of CAVLC decoder , 2003, ASICON 2003.

[2]  Iain E. G. Richardson,et al.  H.264 and MPEG-4 Video Compression: Video Coding for Next-Generation Multimedia , 2003 .

[3]  Jiun-In Guo,et al.  A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[4]  Yeong-Kang Lai,et al.  A simple and cost effective video encoder with memory-reducing CAVLC , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[5]  Ajay Luthra,et al.  Overview of the H.264/AVC video coding standard , 2003, IEEE Trans. Circuits Syst. Video Technol..

[6]  W. Badawy,et al.  Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC) , 2004, IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004..

[7]  Gary J. Sullivan,et al.  Rate-constrained coder control and comparison of video coding standards , 2003, IEEE Trans. Circuits Syst. Video Technol..

[8]  Shawmin Lei,et al.  An entropy coding system for digital HDTV applications , 1991, IEEE Trans. Circuits Syst. Video Technol..

[9]  Liang-Gee Chen,et al.  Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile , 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..