Correct-by-construction layout-centric retargeting of large analog designs

Aggressive design cycles in the semiconductor industry demand a design-reuse principle for analog circuits. The strong impact of layout intricacies on analog circuit performance necessitates design reuse with special focus on layout aspects. This paper presents a computer-aided design tool and the methodology for a layout-centric reuse of large analog intellectual-property blocks. From an existing layout representation, an analog circuit is retargeted to different processes and performances; the corresponding correct-by-construction layouts are generated automatically and have performances comparable to manually crafled layouts. The tool and the methodology are validated on large analog intellectual-properly blocks. While manual re-design and re-layout is known to take weeks: to months, our *use tool-suite achieves comparable performance in hours.

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