Evaluation of multiple-output logic functions using decision diagrams
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[1] Shinobu Nagayama,et al. Compact BDD Representations for Multiple-Output Functions and Their Application , 2001 .
[2] Tsutomu Sasao. Compact SOP representations for multiple-output functions-an encoding method using multiple-valued logic , 2001, Proceedings 31st IEEE International Symposium on Multiple-Valued Logic.
[3] Luciano Lavagno,et al. Synthesis of software programs for embedded control applications , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Rolf Drechsler,et al. Functional simulation using binary decision diagrams , 1997, ICCAD 1997.
[5] S. Yang,et al. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .
[6] Alexander Saldanha,et al. Fast discrete function evaluation using decision diagrams , 1995, ICCAD.
[7] R. Brayton,et al. Software synthesis from synchronous specifications using logic simulation techniques , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).
[8] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[9] Sharad Malik,et al. Fast functional simulation using branching programs , 1995, ICCAD.