A repeater timing model and insertion algorithm to reduce delay in RC tree structures

One method of overcoming wire delay due to long resistive interconnect is to insert repeaters in the line. Analytical expressions describing a CMOS inverter driving an RC load have been integrated into a methodology for inserting repeaters in RC trees. These expressions are based on a short channel I-V model and exhibit less than 10% error. This repeater insertion methodology and its software implementation are described in this paper.

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