A repeater timing model and insertion algorithm to reduce delay in RC tree structures
暂无分享,去创建一个
[1] L.P.P.P. van Ginneken,et al. Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .
[2] Yvon Savaria,et al. Optimal methods of driving interconnections in VLSI circuits , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.
[3] E.G. Friedman,et al. Repeater insertion to reduce delay and power in RC tree structures , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).
[4] V. Adler,et al. Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[5] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[6] Eby G. Friedman,et al. Design of tapered buffers with local interconnect capacitance , 1995, IEEE J. Solid State Circuits.
[7] A. R. Newton,et al. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .
[8] W. C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .
[9] Eby G. Friedman,et al. Repeater design to reduce delay and power in resistive interconnect , 1998 .
[10] Eby G. Friedman,et al. A unified design methodology for CMOS tapered buffers , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[11] Chung-Hu Wu,et al. Accurate speed improvement techniques for RC line and tree interconnections in CMOS VLSI , 1990, IEEE International Symposium on Circuits and Systems.
[12] Richard C. Jaeger,et al. Comments on "An optimized output stage for MOS integrated circuits" [with reply] , 1975 .