Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture

This paper describes a novel low delay 4K 120fps real-time HEVC decoder we have developed with parallel processing architecture that conforms to the HEVC Main 4:2:2 10 profile. It supports the temporal scalable streams required for 4K high frame rate broadcasting and also supports low delay and high bitrate decoding for video transmission. To achieve this support, the decoding processes are parallelized and pipelined at frame level, slice level and Coding Tree Unit row level. The proposed decoder is implemented on three Arria10 series FPGAs operating at 133 and 150MHz, and achieves 300Mbps stream decoding and 37msec end-to-end delay with our concurrently developed 4K 120fps encoder.