On-chip fingerprinting of IC topology for integrity verification

The integrity of integrated circuits (ICs), in particular for detecting malicious add-ons like Hardware Trojans (HTs), have been studied in several recent research papers. The main limit of the proposed techniques so far is that the bias induced by the process variations restrict their efficiency and practicality. Most of those techniques compare two ICs' signatures while trying to get rid of the process variations. In this paper we propose a novel approach which in practice eliminates this limit. We first make the assumption that IC infection is done at a lot level, which is more realistic than models where infections are done on individual circuits. We introduce a variation model for the performance of CMOS structures in real designs which are different from test chips dedicated to the measure of process variations. This model is used to create signatures of lots which are independent of the process variations and is used as a base to define methods allowing to detect HTs and counterfeits in a straightforward way. The model and the methods are validated experimentally on 30 FPGA boards.

[1]  Ingrid Verbauwhede,et al.  Electromagnetic circuit fingerprints for Hardware Trojan detection , 2015, 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC).

[2]  Jie Li,et al.  At-speed delay characterization for IC authentication and Trojan Horse detection , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[3]  Assia Tria,et al.  A high efficiency Hardware Trojan detection technique based on fast SEM imaging , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Miron Abramovici,et al.  Integrated circuit security: new threats and solutions , 2009, CSIIRW '09.

[5]  Mark J. Schervish,et al.  Probability and Statistics ,4th Edition , 2014 .

[6]  Walter L. Smith.  Probability and Statistics , 1959, Nature.

[7]  Farinaz Koushanfar,et al.  A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.

[8]  Mark Mohammad Tehranipoor,et al.  BISA: Built-in self-authentication for preventing hardware Trojan insertion , 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[9]  Paolo A. Aseron,et al.  Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency , 2010, IEEE Custom Integrated Circuits Conference 2010.

[10]  S. Kosonocky,et al.  Fluctuation limits & scaling opportunities for CMOS SRAM cells , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[11]  Kaushik Roy,et al.  Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[12]  Christos A. Papachristou,et al.  MERO: A Statistical Approach for Hardware Trojan Detection , 2009, CHES.

[13]  Berk Sunar,et al.  Trojan Detection using IC Fingerprinting , 2007, 2007 IEEE Symposium on Security and Privacy (SP '07).

[14]  Franco Stellari,et al.  Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[15]  Keith A. Bowman,et al.  Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[16]  Sylvain Guilley,et al.  Method taking into account process dispersion to detect hardware Trojan Horse by side-channel analysis , 2016, Journal of Cryptographic Engineering.

[17]  Michael Hutter,et al.  EM-based detection of hardware trojans on FPGAs , 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[18]  Mark Mohammad Tehranipoor,et al.  RON: An on-chip ring oscillator network for hardware Trojan detection , 2011, 2011 Design, Automation & Test in Europe.

[19]  Chip-Hong Chang,et al.  Cluster-based distributed active current timer for hardware Trojan detection , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[20]  Mark Mohammad Tehranipoor,et al.  Experimental analysis of a ring oscillator network for hardware Trojan detection in a 90nm ASIC , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Mark Mohammad Tehranipoor,et al.  An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities , 2011, IEEE Transactions on Information Forensics and Security.

[22]  Morteza Saheb Zamani,et al.  A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust , 2015, J. Circuits Syst. Comput..

[23]  Mark Mohammad Tehranipoor,et al.  Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain , 2014, Proceedings of the IEEE.

[24]  Yao-Wen Chang,et al.  Floorplan and power/ground network co-synthesis for fast design convergence , 2006, ISPD '06.