Architecture-Based Regression Verification of AADL Specifications

Design artifacts of dependable embedded systems, and the systems themselves, are subjected to a number of modifications during the development process. Verified artifacts that subsequently are modified must necessarily be re-verified to ensure that no faults have been introduced in response to the modification. We collectively call this type of verification as regression verification. Studies show that regression testing alone consumes a vast amount of the total development cost. This is likely a result of unnecessary verification of parts that are not affected by the modification. In this paper, we propose an architecture-based selective regression verification technique for the development process of dependable embedded systems specified in the Architecture Analysis and Design Language (AADL). The selection of necessary regression verification sequences is based on the concept of specification slicing through System Dependence Graphs (SDGs). This allows for the avoidance of unnecessary re-verification, and thereby unnecessary costs.