Managing QoS flows at task level in NoC-based MPSoCs

The use of NoCs in complex MPSoCs is a reality in academic researches and industrial designs. A lot of research effort has been conducted in the last years in NoC and MPSoC designs, but few works address the gap between the NoC infrastructure and the MPSoC software applications. An important issue in MPSoC design is QoS, since applications running in such systems may have tight timing constraints, as video processing or fast communication protocols. This work bridges the hardware/software gap, exploring the integration of low-level NoC services into an application programming interface (API). Such API hides the interconnection complexity from programmer and provides efficient design space exploration to meet the QoS application requirements. Results shows that, even with the huge available bandwidth offered by NoCs, such interconnection architecture is not capable to meet QoS constraints when flows compete for common resources inside the NoC. Using the priority scheme developed in this work, applications executing in the MPSoC achieve the performance requirements. This work highlights the need to integrate NoC and MPSoC design efforts in a unified framework.

[1]  Gerhard Fettweis,et al.  A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips , 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

[2]  Orlando Moreira,et al.  Online resource management in a multiprocessor with a network-on-chip , 2007, SAC '07.

[3]  David Castells-Rufas,et al.  xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures , 2008, 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008).

[4]  Fernando Gehm Moraes,et al.  HeMPS - a framework for NoC-based MPSoC generation , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[5]  Henry Hoffmann,et al.  On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.

[6]  Fernando Gehm Moraes,et al.  HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..

[7]  Fernando Moraes,et al.  A New Router Architecture for High-Performance Intrachip Networks , 2008 .

[8]  Xiaola Lin,et al.  Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers , 1994, IEEE Trans. Parallel Distributed Syst..

[9]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[10]  Sudhakar Yalamanchili,et al.  Interconnection Networks , 2011, Encyclopedia of Parallel Computing.

[11]  J. van Meerbergen,et al.  Novel QoS model for mapping of MPEG-4 coding onto MP-NoC , 2005, Proceedings of the Ninth International Symposium on Consumer Electronics, 2005. (ISCE 2005)..