论文信息 - A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input

A programmable on-chip picosecond jitter-measurement circuit without a reference-clock input

An on-chip jitter measurement circuit in 0.18 /spl mu/m CMOS is demonstrated, using a combination of a programmable delay line, interleaving PFD, and programmable charge pumps. The method does not require a reference clock. Interleaving PFD minimizes bias errors. Measurement linearity is 3.5 /spl mu/V/ps with an error of 1.03ps/sub rms/ for a 2GHz clock.

[1] Tawfik Rahal-Arabi. Design & validation of the Pentium® III and Pentium® 4 processors power delivery , 2002, VLSIC 2002.

[2] H. Tsuchida,et al. Pulse timing stabilization of a mode-locked Cr:LiSAF laser. , 1999, Optics letters.

[3] M. Takamiya,et al. On-chip jitter-spectrum-analyzer for high-speed digital designs , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[4] T. Rahal-Arabi,et al. Design and validation of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors power delivery , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).