Overview of Heterogeneous Integrations
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[1] N. Jokerst. Hybrid Integrated Optoelectronics: Thin Film Devices Bonded to Host Substrates , 1997 .
[2] R. Aschenbrenner,et al. Material and process trends for moving from FOWLP to FOPLP , 2015, 2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC).
[4] Chueh-An Hsieh,et al. Fan-out technologies for WiFi SiP module packaging and electrical performance simulation , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
[5] Yu-Sheng Hsieh,et al. 3D heterogeneous integration structure based on 40 nm- and 0.18 µm-technology nodes , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
[6] D. Ruffieux,et al. Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[7] Paresh Limaye,et al. Zero-level packaging for (RF-)MEMS implementing TSVs and metal bonding , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
[8] Chih-Chun Hsu,et al. De-sensitization Design and Analysis for Highly Integrated RFSoC and DRAM Stacked-Die Design , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[9] John H. Lau,et al. Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.
[10] Koichi Tanaka,et al. Development of Thinner POP Base Package by Die Embedded and RDL Structure , 2017 .
[11] Eric Beyne,et al. A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[12] Benson Lin,et al. A Novel System in Package with Fan-Out WLP for High Speed SERDES Application , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
[13] Douglas Yu,et al. InFO (Wafer Level Integrated Fan-Out) Technology , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
[15] Chet Palesko,et al. Cost Comparison of Fan-out Wafer-Level Packaging to Embedded Die Packaging , 2017 .
[16] John H. Lau. Patent Issues of Fan-Out Wafer-Level Packaging , 2018 .
[17] Doug Mitchell,et al. 3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency , 2013 .
[18] Vinayak Pandey,et al. Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology , 2017 .
[19] Yong Liu,et al. Modeling for reliability of ultra thin chips in a system in package , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
[20] Elisabete Fernandes,et al. Implementation of Wafer Level Packaging KOZ using SU-8 as Dielectric for the Merging of WL Fan Out to Microfluidic and Biomedical Applications , 2017 .
[21] John H. Lau,et al. 3D IC Heterogeneous Integration by FOWLP , 2018 .
[22] R. Ruby,et al. Wafer-scale packaging for FBAR-based oscillators , 2011, 2011 Joint Conference of the IEEE International Frequency Control and the European Frequency and Time Forum (FCS) Proceedings.
[23] J. Lau,et al. Development of chip-first and die-up fan-out wafer level packaging , 2017, 2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
[24] M. Brillhart,et al. Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[25] Frank D. Egitto,et al. 3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics , 2013 .
[26] Shin-Puu Jeng,et al. 3D Heterogeneous Integration with Multiple Stacking Fan-Out Package , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[27] Robert N. Dean,et al. Using SPICE to Model Nonlinearities Resulting from Heterogeneous Integration of Complex Systems , 2017 .
[28] Shin-Puu Jeng,et al. Reliability evaluation of a CoWoS-enabled 3D IC package , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[29] Yuan Xie,et al. Cost-effective design of scalable high-performance systems using active and passive interposers , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[30] R. Aschenbrenner,et al. Foldable Fan-Out Wafer Level Packaging , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
[32] M. Kao,et al. Through-Silicon Hole Interposers for 3-D IC Integration , 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[33] John H. Lau,et al. Process integration of 3D Si interposer with double-sided active chip attachments , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[34] John H. Lau,et al. Fan-Out Wafer-Level Packaging , 2018 .
[35] B. Banijamali,et al. Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.
[36] Li Zhang,et al. A novel wafer level packaging for white light LED , 2013, 2013 14th International Conference on Electronic Packaging Technology.
[37] John H. Lau,et al. Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs) , 2017 .
[38] C S Premachandran,et al. Development of a Cu/Low-$k$ Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[39] Youngtak Lee,et al. Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids , 2017 .
[40] Tai Chong Chai,et al. Development of Large Die Fine-Pitch Cu/Low- $k$ FCBGA Package With Through Silicon via (TSV) Interposer , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[41] Hongbin Yu,et al. Integration of magnetic materials into package RF and power inductors on organic substrates for system in package (SiP) applications , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).
[42] Gabriel Pares,et al. Flip chip reliability and design rules for SIP module , 2017 .
[43] D. Danovitch,et al. Controlling Underfill Lateral Flow to Improve Component Density in Heterogeneously Integrated Packaging Systems , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[44] Wei Pang,et al. A Temperature-Stable Film Bulk Acoustic Wave Oscillator , 2008, IEEE Electron Device Letters.
[46] Mohan Nagar,et al. Ultra large System-in-Package (SiP) module and novel packaging solution for networking applications , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[48] Ji-Jan Chen,et al. Unified methodology for heterogeneous integration with CoWoS technology , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[49] S. Voges,et al. Non-Destructive Testing for System-in-Package Integrity Analysis , 2017 .
[51] Bob Chylak,et al. Wire Bonding Looping Solutions for High Density System-in-Package (SiP) , 2017 .
[53] C.K. Yu,et al. Reliability Study of Large Fan-Out BGA Solution on FinFET Process , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[54] Jinyoung Kim,et al. Fan-Out Panel Level Package with Fine Pitch Pattern , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[55] Kuo-Shu Kao,et al. Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[56] V. N. Sekhar,et al. Wafer level packaging of RF MEMS devices using TSV interposer technology , 2012, 2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
[57] K. Lang,et al. Chip embedding technology developments leading to the emergence of miniaturized system-in-packages , 2010, 18th European Microelectronics & Packaging Conference.
[58] D. Xiao,et al. LED packaging using silicon substrate with cavities for phosphor printing and copper-filled TSVs for 3D interconnection , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
[59] Rao Tummala,et al. 2.5D Glass Panel Embedded (GPE) Packages with Better I/O Density, Performance, Cost and Reliability than Current Silicon Interposers and High-Density Fan-Out Packages , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[60] K. Ohno,et al. Novel stacked CMOS image sensor with advanced Cu2Cu hybrid bonding , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).
[61] Stephan Borel,et al. A Novel Structure for Backside Protection Against Physical Attacks on Secure Chips or SiP , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[62] A. Kumar,et al. Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[63] Nick Renaud-Bezot. Size Matters – Embedding as an Enabler of Next-Generation SiPs , 2013 .
[64] John H. Lau,et al. Chip on Board: Technologies for Multichip Modules , 1995 .
[65] Kilsoo Kim,et al. Study of Advanced Fan-Out Packages for Mobile Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[66] J. Lau,et al. A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications , 2008, 2008 58th Electronic Components and Technology Conference.
[67] John H Lau,et al. Fan-out wafer-level packaging for 3D IC heterogeneous integration , 2018, 2018 China Semiconductor Technology International Conference (CSTIC).
[68] R. Mahajan,et al. Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
[69] C. Selvanayagam,et al. Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps , 2009, IEEE Transactions on Advanced Packaging.
[70] Hugo Gamboa,et al. Heterogeneous Integration Challenges Within Wafer Level Fan-Out SiP for Wearables and IoT , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[71] Vempati Srinivasa Rao,et al. Process Development and Reliability of Microbumps , 2010, IEEE Transactions on Components and Packaging Technologies.
[72] Kilsoo Kim,et al. Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[73] John H. Lau,et al. Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps , 2009, 2009 59th Electronic Components and Technology Conference.
[74] Madhavan Swaminathan,et al. A System-in-Package Based Energy Harvesting for IoT Devices with Integrated Voltage Regulators and Embedded Inductors , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[75] Clark Hu,et al. Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology , 2017, IEEE Transactions on Electron Devices.
[76] V. N. Sekhar,et al. Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.
[77] S.B. Park,et al. Design Guideline of 2.5D Package with Emphasis on Warpage Control and Thermal Management , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[78] J. Lau,et al. Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[79] Tzu-Chun Tang,et al. InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[80] Xiaowu Zhang,et al. Development of 3-D Silicon Module With TSV for System in Packaging , 2010, IEEE Transactions on Components and Packaging Technologies.
[82] Heng-Chieh Chien,et al. Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[83] John Knickerbocker,et al. Heterogeneous Integration Technology Demonstrations for Future Healthcare, IoT, and AI Computing Solutions , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[84] John H. Lau,et al. Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking , 2009, 2009 59th Electronic Components and Technology Conference.
[85] Frank D. Egitto,et al. 3D Integration of System-in-Package (SiP) Using Organic In terposer: Toward SiP-Interposer-SiP for High-End Electronics , 2013 .
[86] Seung Wook Yoon,et al. Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[87] Jinglin Shi,et al. High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP) , 2010, IEEE Transactions on Advanced Packaging.
[88] A. Hanna,et al. Extremely Flexible (1mm Bending Radius) Biocompatible Heterogeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (<6 µm) and Reliable Flexible Cu-Based Interconnects , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[89] M. Kaynak,et al. Development of a Multi-project Fan-Out Wafer Level Packaging Platform , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
[90] Seung Wook Yoon,et al. Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[92] Dale Ibbotson,et al. Enabling the 2.5D Integration , 2012 .
[93] Ming Li,et al. Package Co-design of a Fully Integrated Multimode 76-81GHz 45nm RFCMOS FMCW Automotive Radar Transceiver , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[94] R. Chaware,et al. Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[95] John H. Lau,et al. Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-in-package (SiP) , 2012, Microelectron. Reliab..
[96] Jing Li,et al. Design and analysis of 3D stacked optoelectronics on optical printed circuit boards , 2008, SPIE OPTO.
[97] Andy Heinig,et al. Heterogeneous Interposer Based Integration of Chips with Copper Pillars and C4 Balls to Achieve High Speed Interfaces for ADC Application , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
[98] Yoshihiro Nakata,et al. Planar Antenna for Terahertz Application in Fan Out Wafer Level Package , 2017 .
[100] John H. Lau,et al. Embedded 3D Hybrid IC Integration System-in-Package (SiP) for Opto-Electronic Interconnects in Organic Substrates , 2010 .
[101] J. Chen,et al. Design, Fabrication and Characterization of TSV Interposer Integrated 3D Capacitor for SIP Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[102] Yu-Min Lin,et al. An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications , 2019, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
[103] John H. Lau,et al. TSV manufacturing yield and hidden costs for 3D IC integration , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
[104] Rong Zhang,et al. Moldless encapsulation for LED wafer level packaging using integrated DRIE trenches , 2012, Microelectron. Reliab..
[105] G. Cibrario,et al. 3D Integration of CMOS image sensor with coprocessor using TSV last and micro-bumps technologies , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[106] Xin Sun,et al. Modeling and Design of a 3D Interconnect Based Circuit Cell Formed with 3D SiP Techniques Mimicking Brain Neurons for Neuromorphic Computing Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[107] Chun-Wei Chang,et al. Signal and Power Integrity Analysis of InFO Interconnect for Networking Application , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[108] R. Aschenbrenner,et al. Panel Level Packaging - A View Along the Process Chain , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[109] Hiroshi Takahashi,et al. A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[110] Curtis Zwenger,et al. Chip Stackable, Ultra-thin, High-Flexibility 3D FOWLP (3D SWIFT® Technology) for Hetero-Integrated Advanced 3D WL-SiP , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[111] Daquan Yu,et al. Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Packaging Technology for Multi-chip and 3D System Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[112] J. Lau,et al. Thermal management of 3D IC integration with TSV (through silicon via) , 2009, 2009 59th Electronic Components and Technology Conference.
[113] Sheng-Tsai Wu,et al. Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW) , 2011 .
[114] Pascal Couderc,et al. Stacking of known good rebuilt wafers for high performance memory and SiP , 2013 .
[115] D. S. Wills,et al. The heterogeneous integration of optical interconnections into integrated microsystems , 2003 .
[116] Saptadeep Pal,et al. Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
[117] Sheng-Tsai Wu,et al. Thermal and mechanical design and analysis of 3D IC interposer with double-sided active chips , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.
[118] J. Lau,et al. Fan-Out Wafer-Level Packaging for Heterogeneous Integration , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[119] John H. Lau,et al. Redistribution Layers (RDLs) for 2.5D/3D IC Integration , 2013 .
[120] Chin-Li Kao,et al. Wafer Warpage Experiments and Simulation for Fan-Out Chip on Substrate , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
[121] Li Zhang,et al. A study of novel wafer level LED package based on TSV technology , 2012, 2012 13th International Conference on Electronic Packaging Technology & High Density Packaging.
[122] B. Banijamali,et al. Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[124] Albert Lan,et al. Alternative 3D Small form Factor Methodology of System in Package for IoT and Wearable Devices Application , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
[125] Mohan Nagar,et al. 3D SiP with Organic Interposer for ASIC and Memory Integration , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
[126] Jürgen Becker,et al. Multiprocessor System-on-Chip - Hardware Design and Tool Integration , 2011, Multiprocessor System-on-Chip.
[127] Dan Oh,et al. Low Cost Si-Less RDL Interposer Package for High Performance Computing Applications , 2018, 2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
[128] F. X. Che,et al. Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI) , 2017, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC).