Logic Synthesis for Field-Programmable Gate Arrays

Preface. Part I: Introduction. 1. Introduction. 2. Background. Part II: Look-up table (LUT) architectures. 3. Mapping computational logic. 4. Logic optimization. 5. Complexity issues. 6. Mapping sequential logic. 7. Performance directed synthesis. Part III: Multiplexor-based architectures. 8. Mapping combinational logic. Part IV: Conclusions. 10. Conclusions. References. Index.