A 33mb/s Data Synchronizing Phase-locked-loop Circuit

data pulses, generates a continuous chain of time windows for pulse capture. To minimize capture errors in jittering data, the window is centered about the mean bit position via a delay of exactly one half of the VCO period placed at the phase coniparator input. The delay line and VCO were designed t o be nearly identically to obtain precide matching, each employing a ring oscillator and an ECL programmable-modulus counter; Figures 1 and 2. The delay line ring oscillator, with current (and therefore frequency) equal to that of the VCO ring oscillator, is energized by the incoming data pulse and stopped once the counter reaches the half modulus point. The counter then issues an output pulse and is reset. Counter moduli are stepped in factors of two from M = 2 to M = 64 to produce a net 96 : l operating range, while requiring only a 3 : l frequency range of the ring oscillators; Figure 3. Timing accuracy of the delay line has been achieved to within Ins at 24Mb/s operating rate.