LOW-POWER 2D MOTION ESTIMATION ARCHITECTURE WITH COMPLEMENTARY EMBEDDED MEMORY BANKS
暂无分享,去创建一个
[1] Hsueh-Ming Hang,et al. A comparison of block-matching algorithms mapped to systolic-array implementation , 1997, IEEE Trans. Circuits Syst. Video Technol..
[2] Kwyro Lee,et al. Charge recycling differential logic (CRDL) for low power application , 1996 .
[3] Leonardo Chiariglione. MPEG and multimedia communications , 1997, IEEE Trans. Circuits Syst. Video Technol..
[4] A. Anesko,et al. A 14 GOPS programmable motion estimator for H.26x video coding , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
[5] I. Tamitani,et al. A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking , 1997, IEEE J. Solid State Circuits.
[6] Matthias Schöbinger,et al. VLSI architecture for a flexible block matching processor , 1995, IEEE Trans. Circuits Syst. Video Technol..
[7] Anantha P. Chandrakasan,et al. Low-power CMOS digital design , 1992 .
[8] Masahiko Yoshimoto,et al. A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search , 1995 .
[9] Kenneth Y. Yun,et al. A low-power VLSI architecture for full-search block-matching motion estimation , 1998, IEEE Trans. Circuits Syst. Video Technol..