Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC

In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their design framework for intellectual property (IP) cores in system-on-chip (SoC). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are a regular tile structure, spare modules and bypass wires for fault avoidance, and a configuration mechanism for singlecycle reconfiguration. In addition, we utilize routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGAs and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 1.82 times the area and 1.11 times the delay compared with traditional island-style FPGAs. At the same time, our FPGA shows a higher fault tolerant performance. key words: fault tolerant, FPGA, IP-core

[1]  Kenneth B. Kent,et al.  Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[2]  John M. Emmert,et al.  A survey of fault tolerant methodologies for FPGAs , 2006, TODE.

[3]  Luigi Carro,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs , 2006 .

[4]  Guy Lemieux,et al.  Analytical Framework for Switch Block Design , 2002, FPL.

[5]  Masahiro Iida,et al.  Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration , 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[6]  Masahiro Iida,et al.  A novel physical defects recovery technique for FPGA-IP cores , 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

[7]  Luigi Carro,et al.  Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing) , 2006 .

[8]  Hideo Ito,et al.  Defect and fault tolerance SRAM-based FPGAs by shifting the confoguration data , 2000 .

[9]  Jason Luu,et al.  VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2009, FPGA '09.

[10]  Luca Sterpone.  Electronics System Design Techniques for Safety Critical Applications , 2009, Lecture Notes in Electrical Engineering.

[11]  M. J. Easton,et al.  Cross-Platform .NET Development: Using Mono, Portable.NET, and Microsoft .NET , 2004, Apress.

[12]  Wayne Luk,et al.  A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications , 2008, TRETS.

[13]  Kenneth B. Kent,et al.  VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2011, TRETS.

[14]  RoseJonathan,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[15]  Vaughn Betz,et al.  Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.

[16]  Masahiro Iida,et al.  FPGA Design Framework Combined with Commercial VLSI CAD , 2013, IEICE Trans. Inf. Syst..

[17]  Jonathan Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[18]  Russell Tessier,et al.  Tolerating operational faults in cluster-based FPGAs , 2000, FPGA '00.

[19]  Masahiro Koga,et al.  An Easily Testable Routing Architecture and Prototype Chip , 2012, IEICE Trans. Inf. Syst..

[20]  Masahiro Iida,et al.  Defect-robust FPGA architectures for intellectual property cores in system LSI , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.