Trade-off between reliability and program time in 40nm TaOx-based Resistive random access memory (ReRAM) is experimentally investigated. By evaluating bit error rate (BER) and the current distributions, the complicated trade-off among Set/Reset cycles, reset voltage (VRESET) and with or without verify are investigated. At lower Set/Reset cycles, the current window is enhanced by introducing Set/Reset cycles and increasing VRESET. However, at higher Set/Reset cycles, the excessive stress caused by the verify and high VRESET increases BER. Because of this "twisted" characteristics, verify should not be performed at higher Set/Reset cycles. To explain these complicated errors, the physical model based on oxygen vacancy (Vo), diffusion is described. Finally, the system-level solution to minimize errors by dynamically co-optimizing ECC strength, verify cycles and the Reset voltage based on Set/Reset cycles is proposed.