Framework for architecture-independent run-time reconfigurable applications

Configurable Computing Machines (CCMs) have emerged as a technology with the computational benefits of custom ASICs as well as the flexibility and reconfigurability of general-purpose microprocessors. Significant effort from the research community has focused on techniques to move this reconfigurability from a rapid application development tool to a run-time tool. This requires the ability to change the hardware design while the application is executing and is known as Run-Time Reconfiguration (RTR). Widespread acceptance of run-time reconfigurable custom computing depends upon the existence of high-level automated design tools. Such tools must reduce the designers effort to port applications between different platforms as the architecture, hardware, and software evolves. A Java implementation of a high-level application framework, called Janus, is presented here. In this environment, developers create Java classes that describe the structural behavior of an application. The framework allows hardware and software modules to be freely mixed and interchanged. A compilation phase of the development process analyzes the structure of the application and adapts it to the target platform. Janus is capable of structuring the run-time behavior of an application to take advantage of the memory and computational resources available.

[1]  Ranga Vemuri,et al.  An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures , 1998, IPPS/SPDP Workshops.

[2]  Rob Gordon,et al.  Essential Jni: Java Native Interface , 1998 .

[3]  Peter M. Athanas,et al.  A run-time reconfigurable engine for image interpolation , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[4]  I. Daubechies,et al.  Biorthogonal bases of compactly supported wavelets , 1992 .

[5]  Brad Hutchings,et al.  RRANN: the run-time reconfiguration artificial neural network , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[6]  Peter M. Athanas,et al.  Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[7]  Ivar Jacobson,et al.  The unified modeling language reference manual , 2010 .

[8]  Brad L. Hutchings,et al.  JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[9]  Brad L. Hutchings,et al.  Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs , 1996, J. VLSI Signal Process..

[10]  Tsuyoshi Isshiki,et al.  Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[11]  Stephen M. Scalera,et al.  The design and implementation of a context switching FPGA , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[12]  Steven Trimberger,et al.  A time-multiplexed FPGA , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[13]  Mark Jones,et al.  Implementing an API for distributed adaptive computing systems , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[14]  I. Daubechies.  Orthonormal bases of compactly supported wavelets , 1988 .

[15]  Leonard A. Ferrari,et al.  An efficient spline basis for multi-dimensional applications: image interpolation , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[16]  Chandra Tan,et al.  Automatic Mapping of Khoros-based Applications to Adaptive Computing Systems , 1999 .

[17]  G. Vijayan.  Partitioning logic on graph structures to minimize routing cost , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Guy L. Steele,et al.  The Java Language Specification , 1996 .

[19]  Peter Athanas,et al.  Spatiotemporal partitioning of computational structures onto configurable computing machines , 1998, Other Conferences.