Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.

[1]  William J. Bowhill,et al.  Design of High-Performance Microprocessor Circuits , 2001 .

[2]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[3]  Magdy A. Bayoumi,et al.  Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Magdy A. Bayoumi,et al.  Contention reduced/conditional discharge flip-flops for level conversion in CVS systems , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[5]  Young-Hyun Jun,et al.  Conditional-capture flip-flop for statistical power reduction , 2001, IEEE J. Solid State Circuits.

[6]  James Tschanz,et al.  Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.

[7]  Resve Saleh,et al.  Analysis and Design of Digital Integrated Circuits , 1983 .

[8]  V.G. Oklobdzija,et al.  Improved sense-amplifier-based flip-flop: design and measurements , 2000, IEEE Journal of Solid-State Circuits.

[9]  L. Heller,et al.  Cascode voltage switch logic: A differential CMOS logic family , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[10]  A. Meyers.  Reading , 1999, Language Teaching.

[11]  Jan M. Rabaey,et al.  Digital Integrated Circuits , 2003 .

[12]  Rong Luo,et al.  High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[13]  Tarek Darwish,et al.  High-performance and low-power conditional discharge flip-flop , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Peiyi Zhao,et al.  Low power and high speed explicit-pulsed flip-flops , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[15]  Dennis Sylvester,et al.  High performance level conversion for dual V/sub DD/ design , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  J. Tschanz,et al.  Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[17]  H. Arakida,et al.  A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[18]  Keith A. Bowman,et al.  Variation-tolerant circuits: circuit solutions and techniques , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[19]  J. Tschanz,et al.  Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[20]  Borivoje Nikolic,et al.  Level conversion for dual-supply systems , 2004 .

[21]  Kaushik Roy,et al.  Self–precharging flip–flop (SPFF): A new level converting flip–flop , 2002 .

[22]  M. Sachdev,et al.  Dual supply voltage clocking for 5 GHz 130 nm integer execution core , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[23]  Enrico Macii,et al.  Designing low-power circuits: practical recipes , 2001 .

[24]  Dennis Sylvester,et al.  Analysis and design of level-converting flip-flops for dual-V/sub dd//V/sub th/ integrated circuits , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

[25]  R. Stephenson.  A and V , 1962, The British journal of ophthalmology.