Massively multi-topology sizing of analog integrated circuits

This paper demonstrates a system that performs multi-objective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, MOJITO, which searches through 3500 topologies defined by a hierarchically-organized set of 30 analog blocks. This paper improves MOJITO's results quality via three key extensions. First, it enlarges the block library to enable symmetrical transconductance amplifiers and more. Second, it improves initial topology diversity via optimization-based constraint satisfaction. Third, it maintains topology diversity during search via a novel multi-objective selection mechanism, dubbed TAPAS. MO-JITO+TAPAS is demonstrated on a problem with 6 objectives, returning a tradeoff holding 17438 nondominated designs. The tradeoff is comprised of 152 unique topologies that include the newly-introduced topologies. 59 designs across 12 topologies designs outperform an expert-designed reference circuit.

[1]  Georges G. E. Gielen,et al.  WATSON: design space boundary exploration and model generation for analog and RFIC design , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Ranga Vemuri,et al.  Topology synthesis of analog circuits based on adaptively generated building blocks , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[3]  Qingfu Zhang,et al.  MOEA/D: A Multiobjective Evolutionary Algorithm Based on Decomposition , 2007, IEEE Transactions on Evolutionary Computation.

[4]  Gregory Hornby,et al.  ALPS: the age-layered population structure for reducing the problem of premature convergence , 2006, GECCO.

[5]  Trent McConaghy,et al.  Genetic Programming in Industrial Analog CAD: Applications and Challenges , 2006 .

[6]  W. Sansen Challenges in analog IC design submicron CMOS technologies , 1996, 1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings.

[7]  Christofer Toumazou,et al.  ISAID-a methodology for automated analog IC design , 1990, IEEE International Symposium on Circuits and Systems.

[8]  Rob A. Rutenbar,et al.  Computer-Aided Design of Analog Integrated Circuits and Systems , 2002 .

[9]  DebK.,et al.  A fast and elitist multiobjective genetic algorithm , 2002 .

[10]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[11]  Michiel Steyaert,et al.  Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[12]  John R. Koza Genetic Programming III - Darwinian Invention and Problem Solving , 1999, Evolutionary Computation.

[13]  Willy Sansen,et al.  analog design essentials , 2011 .

[14]  P. P. Chakrabarti,et al.  A synthesis system for analog circuits based on evolutionary search and topological reuse , 2005, IEEE Transactions on Evolutionary Computation.

[15]  P.R. Gray,et al.  OPASYN: a compiler for CMOS operational amplifiers , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Domine Leenaerts,et al.  DARWIN: CMOS opamp Synthesis by Means of a Genetic Algorithm , 1995, 32nd Design Automation Conference.

[17]  Kurt Antreich,et al.  The sizing rules method for analog integrated circuit design , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[18]  John R. Koza,et al.  Genetic programming - on the programming of computers by means of natural selection , 1993, Complex adaptive systems.

[19]  Christofer Toumazou,et al.  The invention of CMOS amplifiers using genetic programming and current-flow analysis , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Rob A. Rutenbar,et al.  Integer programming based topology selection of cell-level analog circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  H. Wallinga,et al.  SEAS: a simulated evolution approach for analog circuit synthesis , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[22]  Rob A. Rutenbar,et al.  OASYS: a framework for analog circuit synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..